《DJ Online》Advanced Packaging Drives Silicon Wafers from Substrate to Key Material Platform

2026/05/07

MoneyDJ News

May 5, 2026

Author: Wan Huiwen

AI is driving a new round of structural changes in the semiconductor industry. Beyond the widely discussed GPUs, ASICs, HBMs, and advanced packaging, from the upstream materials perspective, AI-driven advanced processes are raising the bar for "material quality, wafer size, heat dissipation, and heterogeneous integration" across the entire semiconductor manufacturing chain. This is also leading the silicon wafer industry from relatively standardized basic material supply to higher-tech functional material platforms.

AI servers are driving a surge in computing power demand, significantly increasing data transfer between GPUs, ASICs, and HBMs. Advanced packaging has thus become crucial for improving system performance. Beyond CoWoS and EMIB, and potentially future CoPoS and CoWoP technologies, the underlying goal is to shorten the distance between the chip and memory, reduce transmission power consumption, and increase bandwidth.

However, this shortened distance and increased chip density also bring another problem: a rapid increase in thermal density per unit area. In the past, semiconductor competition focused primarily on process linewidth and transistor density. However, the bottleneck in the AI era is gradually shifting to energy consumption and heat dissipation. In other words, future computing power will depend not only on how fast chips are manufactured, but also on the system's ability to supply power, dissipate heat, and operate stably.

This is also changing the role of the silicon wafer industry. Previously, silicon wafers were largely seen as standardized substrates, but in advanced AI processes and packaging architectures, wafer materials may play a more diverse role, including high-quality logic and memory wafers, thick epitaxial wafers for power devices, SOI wafers, and even future interposer and heat dissipation-related material platforms.

From an application perspective, the initial wave of demand driven by AI data centers will still be concentrated in high-end logic, memory, and advanced packaging. GPUs, ASICs, and HBMs already require high-quality wafers; as chip sizes increase and packaging structures become more complex, the requirements for wafer flatness, defect control, electrical consistency, and thermal stability will become even more stringent. For silicon wafer fabs, this means that customers in advanced processes will have increasingly higher requirements for material specifications.

In the longer term, advanced packaging may open up new roles for silicon wafer materials. Current market discussions about CoWoS, CoPoS, CoWoP, or glass substrates seem to reflect competition among packaging plants, wafer foundries, substrate manufacturers, and panel manufacturers. However, the essence is a search for the most suitable "intermediate platform" to support high-performance chips. This intermediate platform could be silicon, glass, silicon carbide, or other materials. If crystalline materials remain dominant in the intermediate layer in the future, silicon wafer fabs will not only supply chip substrates but may also enter the market for key materials in advanced packaging.

Under this trend, the silicon wafer industry can move in three directions. Market analysts predict that the traditional silicon wafer market will grow steadily with semiconductor demand, with a compound annual growth rate (CAGR) of 4-6%; SOI wafers, suitable for CPO applications, will see a CAGR of 13-17%; and third-generation semiconductor materials will benefit from power, communication, and heat dissipation demands, with a CAGR of 9-22%.

Currently, major domestic silicon wafer manufacturers, including GlobalWafers (6488), Taisun Technology (3532), and Wafer Works (6182), are actively developing advanced packaging technologies. GlobalWafers' 12-inch high-end products are widely used in advanced process technologies, and its 12-inch SiC wafers are also addressing the thermal performance requirements of advanced packaging. Taisun Technology has focused on silicon wafers for AI memory HBM and is also developing CoWoS-related silicon interposers. Wafer Works is developing Photonics-SOI and GaN/X products and is actively sampling to customers, aiming to seize advanced process technology opportunities in conjunction with the opening of its new 12-inch fab this year.

【Disclaimer】
The content of this article only represents the author's personal views and has nothing to do with Creating.
The content, text description and originality have not been verified by this site. This site does not make any guarantee or commitment to this article and all or part of the content, authenticity, completeness, and timeliness. It is for readers' reference only. Please verify the relevant content yourself.

Creating Nano Technologies, Inc.
59 Alley 21 Lane 279, Chung Cheng Road, Yung Kang City, Tainan, TAIWAN
TEL:886-6-2323927 FAX:886-6-2013306 URL: http://www.creating-nanotech.com

BACK TO LIST